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[PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading
From: |
Palmer Dabbelt |
Subject: |
[PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig |
Date: |
Fri, 3 Mar 2023 00:37:38 -0800 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg
can be avoided by using riscv_cpu_cfg().
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/csr.c | 32 +++++++++-----------------------
1 file changed, 9 insertions(+), 23 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 86e183feb3..78c3b6d5f6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -213,9 +213,7 @@ static RISCVException any32(CPURISCVState *env, int csrno)
static int aia_any(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -224,9 +222,7 @@ static int aia_any(CPURISCVState *env, int csrno)
static int aia_any32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_smaia) {
+ if (!riscv_cpu_cfg(env)->ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -253,9 +249,7 @@ static int smode32(CPURISCVState *env, int csrno)
static int aia_smode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -264,9 +258,7 @@ static int aia_smode(CPURISCVState *env, int csrno)
static int aia_smode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -380,9 +372,7 @@ static RISCVException pointer_masking(CPURISCVState *env,
int csrno)
static int aia_hmode(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -391,9 +381,7 @@ static int aia_hmode(CPURISCVState *env, int csrno)
static int aia_hmode32(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_ssaia) {
+ if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -430,9 +418,7 @@ static RISCVException debug(CPURISCVState *env, int csrno)
static RISCVException seed(CPURISCVState *env, int csrno)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- if (!cpu->cfg.ext_zkr) {
+ if (!riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -555,7 +541,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val = env_archcpu(env)->cfg.vlen >> 3;
+ *val = riscv_cpu_cfg(env)->vlen >> 3;
return RISCV_EXCP_NONE;
}
@@ -610,7 +596,7 @@ static RISCVException write_vstart(CPURISCVState *env, int
csrno,
* The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits.
*/
- env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
+ env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
return RISCV_EXCP_NONE;
}
--
2.39.2
- [PULL 42/59] target/riscv: Group all predicate() routines together, (continued)
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(), Palmer Dabbelt, 2023/03/03
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 50/59] target/riscv: Add csr support for svadu, Palmer Dabbelt, 2023/03/03
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 53/59] target/riscv: Export Svadu property, Palmer Dabbelt, 2023/03/03
- [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig,
Palmer Dabbelt <=
- [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s(), Palmer Dabbelt, 2023/03/03
- [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Palmer Dabbelt, 2023/03/03
- [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr(), Palmer Dabbelt, 2023/03/03
- [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03