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[PULL 50/59] target/riscv: Add csr support for svadu
From: |
Palmer Dabbelt |
Subject: |
[PULL 50/59] target/riscv: Add csr support for svadu |
Date: |
Fri, 3 Mar 2023 00:37:31 -0800 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 4 ++++
target/riscv/csr.c | 17 +++++++++++------
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 31537fc05f..3991eab5e5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -450,6 +450,7 @@ struct RISCVCPUConfig {
bool ext_zihintpause;
bool ext_smstateen;
bool ext_sstc;
+ bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8b0d7e20ea..fca7ef0cef 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -747,10 +747,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_HADE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
/* For RV32 */
+#define MENVCFGH_HADE BIT(29)
#define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31)
@@ -763,10 +765,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_HADE MENVCFG_HADE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */
+#define HENVCFGH_HADE MENVCFGH_HADE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b86c1aa6fa..be71c50f09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env,
int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cfg->ext_sstc ? MENVCFG_STCE : 0);
+ (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+ (cfg->ext_svadu ? MENVCFG_HADE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env,
int csrno,
{
RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cfg->ext_sstc ? MENVCFG_STCE : 0);
+ (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+ (cfg->ext_svadu ? MENVCFG_HADE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env,
int csrno,
/*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
+ * henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/
- *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
+ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+ env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env,
int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
- mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+ mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
return ret;
}
- *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
+ *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
@@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env,
int csrno,
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+ uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
+ HENVCFG_HADE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.39.2
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, (continued)
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(), Palmer Dabbelt, 2023/03/03
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 50/59] target/riscv: Add csr support for svadu,
Palmer Dabbelt <=
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 53/59] target/riscv: Export Svadu property, Palmer Dabbelt, 2023/03/03
- [PULL 57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- [PULL 58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s(), Palmer Dabbelt, 2023/03/03
- [PULL 56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Palmer Dabbelt, 2023/03/03
- [PULL 54/59] target/riscv/csr.c: use env_archcpu() in ctr(), Palmer Dabbelt, 2023/03/03
- [PULL 59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig, Palmer Dabbelt, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03
- Re: [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/03/03