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[PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in tra
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc |
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Date: |
Fri, 3 Mar 2023 00:37:00 -0800 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f7ecf1a68..9b2711b94b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
switch (s->sew) {
case MO_16:
case MO_32:
- return has_ext(s, RVF);
+ return s->cfg_ptr->ext_zve32f;
case MO_64:
- return has_ext(s, RVD);
+ return s->cfg_ptr->ext_zve64d;
default:
return false;
}
@@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
switch (s->sew) {
case MO_8:
case MO_16:
- return has_ext(s, RVF);
+ return s->cfg_ptr->ext_zve32f;
case MO_32:
- return has_ext(s, RVD);
+ return s->cfg_ptr->ext_zve64d;
default:
return false;
}
--
2.39.2
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), (continued)
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental, Palmer Dabbelt, 2023/03/03
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh, Palmer Dabbelt, 2023/03/03
- [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D, Palmer Dabbelt, 2023/03/03
- [PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Palmer Dabbelt, 2023/03/03
- [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc,
Palmer Dabbelt <=
- [PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions, Palmer Dabbelt, 2023/03/03
- [PULL 17/59] target/riscv: Indent fixes in cpu.c, Palmer Dabbelt, 2023/03/03
- [PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions, Palmer Dabbelt, 2023/03/03
- [PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64, Palmer Dabbelt, 2023/03/03
- [PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 24/59] target/riscv: Expose properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Palmer Dabbelt, 2023/03/03
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, Palmer Dabbelt, 2023/03/03
- [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check, Palmer Dabbelt, 2023/03/03