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[PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG
From: |
Palmer Dabbelt |
Subject: |
[PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG |
Date: |
Fri, 3 Mar 2023 00:36:45 -0800 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
RISCV_FEATURE_DEBUG will always follow the value defined by
cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 6 +-----
target/riscv/cpu.h | 1 -
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/machine.c | 3 +--
5 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d637b1acd..13e55ec5bd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
- if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ if (cpu->cfg.debug) {
riscv_trigger_init(env);
}
@@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
- if (cpu->cfg.debug) {
- riscv_set_feature(env, RISCV_FEATURE_DEBUG);
- }
-
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.ext_sstc) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ca828424c1..dc62554e14 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,7 +89,6 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_DEBUG
};
/* Privileged specification version */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3a9472a2ff..7ae832e829 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
get_field(env->mstatus_hs, MSTATUS_VS));
}
- if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
+ if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
}
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3cb8d2ffad..e220c4a5fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException debug(CPURISCVState *env, int csrno)
{
- if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ if (riscv_cpu_cfg(env)->debug) {
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index c6ce318cce..4634968898 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
static bool debug_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
- CPURISCVState *env = &cpu->env;
- return riscv_feature(env, RISCV_FEATURE_DEBUG);
+ return cpu->cfg.debug;
}
static int debug_post_load(void *opaque, int version_id)
--
2.39.2
- [PULL 00/59] Fifth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/03/03
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(), Palmer Dabbelt, 2023/03/03
- [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Palmer Dabbelt, 2023/03/03
- [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG,
Palmer Dabbelt <=
- [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP, Palmer Dabbelt, 2023/03/03
- [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(), Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Palmer Dabbelt, 2023/03/03
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental, Palmer Dabbelt, 2023/03/03
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh, Palmer Dabbelt, 2023/03/03