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[PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
From: |
Richard Henderson |
Subject: |
[PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc |
Date: |
Sun, 26 Feb 2023 19:42:02 -1000 |
All remaining uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 9916784e64..0f5b0056f1 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
- TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
+ TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc
*a)
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
- ro = tcg_const_i32(a->rc);
+ ro = tcg_constant_i32(a->rc);
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
@@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
}
@@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \
}
@@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
@@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \
@@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
@@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(32767);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(32767);
tcg_gen_extract_i64(exp, xbh, 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
@@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
--
2.34.1
- [PATCH 29/70] target/microblaze: Avoid tcg_const_* throughout, (continued)
- [PATCH 29/70] target/microblaze: Avoid tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 33/70] target/mips: Avoid tcg_const_* throughout, Richard Henderson, 2023/02/27
- [PATCH 31/70] target/mips: Split out gen_lxr, Richard Henderson, 2023/02/27
- [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld, Richard Henderson, 2023/02/27
- [PATCH 34/70] target/ppc: Split out gen_vx_vmul10, Richard Henderson, 2023/02/27
- [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad, Richard Henderson, 2023/02/27
- [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb, Richard Henderson, 2023/02/27
- [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc, Richard Henderson, 2023/02/27
- [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval, Richard Henderson, 2023/02/27
- [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc,
Richard Henderson <=
- [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc, Richard Henderson, 2023/02/27
- [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc, Richard Henderson, 2023/02/27
- [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S, Richard Henderson, 2023/02/27
- [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206, Richard Henderson, 2023/02/27
- [PATCH 45/70] target/riscv: Avoid tcg_const_*, Richard Henderson, 2023/02/27
- [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation, Richard Henderson, 2023/02/27
- [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed, Richard Henderson, 2023/02/27
- [PATCH 46/70] target/rx: Use tcg_gen_abs_i32, Richard Henderson, 2023/02/27
- [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c, Richard Henderson, 2023/02/27