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[PATCH 2/4] target/riscv/csr.c: simplify mctr()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 2/4] target/riscv/csr.c: simplify mctr() |
Date: |
Fri, 24 Feb 2023 14:45:18 -0300 |
Use riscv_cpu_cfg() to retrieve pmu_num.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3692617d13..0f4aa22a0f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -165,8 +165,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ int pmu_num = riscv_cpu_cfg(env)->pmu_num;
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -175,7 +174,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
- if (!cpu->cfg.pmu_num || ctr_index >= cpu->cfg.pmu_num) {
+ if (!pmu_num || ctr_index >= pmu_num) {
/* The PMU is not enabled or counter is out of range*/
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.39.2
- [PATCH 0/4] RISCVCPUConfig related cleanups, Daniel Henrique Barboza, 2023/02/24
- [PATCH 1/4] target/riscv/csr.c: use env_archcpu() in ctr(), Daniel Henrique Barboza, 2023/02/24
- [PATCH 2/4] target/riscv/csr.c: simplify mctr(),
Daniel Henrique Barboza <=
- [PATCH 3/4] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers, Daniel Henrique Barboza, 2023/02/24
- [PATCH 4/4] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig, Daniel Henrique Barboza, 2023/02/24
- Re: [PATCH 0/4] RISCVCPUConfig related cleanups, Richard Henderson, 2023/02/24
- Re: [PATCH 0/4] RISCVCPUConfig related cleanups, Richard Henderson, 2023/02/24
- Re: [PATCH 0/4] RISCVCPUConfig related cleanups, liweiwei, 2023/02/25