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[PATCH v7 09/10] target/riscv: remove RISCV_FEATURE_MMU
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v7 09/10] target/riscv: remove RISCV_FEATURE_MMU |
Date: |
Wed, 22 Feb 2023 15:52:04 -0300 |
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
the flag directly instead.
With this change the enum is also removed. It is worth noticing that
this enum, and all the RISCV_FEATURES_* that were contained in it,
predates the existence of the cpu->cfg object. Today, using cpu->cfg is
an easier way to retrieve all the features and extensions enabled in the
hart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 4 ----
target/riscv/cpu.h | 7 -------
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 4 ++--
target/riscv/monitor.c | 2 +-
target/riscv/pmp.c | 2 +-
6 files changed, 5 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d321ad28d2..11da920915 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
- if (cpu->cfg.mmu) {
- riscv_set_feature(env, RISCV_FEATURE_MMU);
- }
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3246153db2..fb0f2afe0d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,13 +81,6 @@
#define RVH RV('H')
#define RVJ RV('J')
-/* S extension denotes that Supervisor mode exists, however it is possible
- to have a core that support S mode but does not have an MMU and there
- is currently no bit in misa to indicate whether an MMU exists or not
- so a cpu features bitfield is required, likewise for optional PMP support */
-enum {
- RISCV_FEATURE_MMU,
-};
/* Privileged specification version */
enum {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 292b6b3168..eda2293470 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
mode = PRV_U;
}
- if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf33494945..75a540bfcb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2621,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int
csrno,
static RISCVException read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (!riscv_cpu_cfg(env)->mmu) {
*val = 0;
return RISCV_EXCP_NONE;
}
@@ -2640,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int
csrno,
{
target_ulong vm, mask;
- if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (!riscv_cpu_cfg(env)->mmu) {
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 236f93b9f5..f36ddfa967 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (!riscv_cpu_cfg(env)->mmu) {
monitor_printf(mon, "S-mode MMU unavailable\n");
return;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 205bfbe090..a08cd95658 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
}
if (size == 0) {
- if (riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (riscv_cpu_cfg(env)->mmu) {
/*
* If size is unknown (0), assume that all bytes
* from addr to the end of the page will be accessed.
--
2.39.2
- [PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg(), (continued)
- [PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg(), Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 02/10] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 03/10] target/riscv: allow MISA writes as experimental, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 04/10] target/riscv: remove RISCV_FEATURE_DEBUG, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 05/10] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 06/10] target/riscv: remove RISCV_FEATURE_EPMP, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 07/10] target/riscv: remove RISCV_FEATURE_PMP, Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 08/10] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(), Daniel Henrique Barboza, 2023/02/22
- [PATCH v7 09/10] target/riscv: remove RISCV_FEATURE_MMU,
Daniel Henrique Barboza <=
- [PATCH v7 10/10] target/riscv/cpu: remove CPUArchState::features and friends, Daniel Henrique Barboza, 2023/02/22