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[PULL 7/9] target/riscv: Smepmp: Skip applying default rules when addres
From: |
Palmer Dabbelt |
Subject: |
[PULL 7/9] target/riscv: Smepmp: Skip applying default rules when address matches |
Date: |
Fri, 17 Feb 2023 09:52:01 -0800 |
From: Himanshu Chauhan <hchauhan@ventanamicro.com>
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch skips applying default rules when matching address range
is found. It returns the index of the match PMP entry.
Fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb)
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230209055206.229392-1-hchauhan@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/pmp.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d1126a6066..4bc4113531 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -441,9 +441,12 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
}
}
- if ((privs & *allowed_privs) == privs) {
- ret = i;
- }
+ /*
+ * If matching address range was found, the protection bits
+ * defined with PMP must be used. We shouldn't fallback on
+ * finding default privileges.
+ */
+ ret = i;
break;
}
}
--
2.39.0
- [PULL 0/9] Fourth RISC-V PR for QEMU 8.0, Palmer Dabbelt, 2023/02/17
- [PULL 2/9] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel(), Palmer Dabbelt, 2023/02/17
- [PULL 1/9] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel(), Palmer Dabbelt, 2023/02/17
- [PULL 3/9] hw/riscv/boot.c: make riscv_load_initrd() static, Palmer Dabbelt, 2023/02/17
- [PULL 5/9] target/riscv: Remove privileged spec version restriction for RVV, Palmer Dabbelt, 2023/02/17
- [PULL 6/9] MAINTAINERS: Add some RISC-V reviewers, Palmer Dabbelt, 2023/02/17
- [PULL 7/9] target/riscv: Smepmp: Skip applying default rules when address matches,
Palmer Dabbelt <=
- [PULL 8/9] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state(), Palmer Dabbelt, 2023/02/17
- [PULL 4/9] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/02/17
- [PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf, Palmer Dabbelt, 2023/02/17
- Re: [PULL 0/9] Fourth RISC-V PR for QEMU 8.0, Peter Maydell, 2023/02/21