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[PATCH v5 4/4] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholde
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v5 4/4] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder |
Date: |
Wed, 15 Feb 2023 17:59:11 -0300 |
From: Christoph Muellner <cmuellner@linux.com>
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn32.decode | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3788f86528..1aebd37572 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -134,6 +134,7 @@ addi ............ ..... 000 ..... 0010011 @i
slti ............ ..... 010 ..... 0010011 @i
sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
+# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
slli 00000. ...... ..... 001 ..... 0010011 @sh
--
2.39.1