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[PATCH v2 02/11] target/riscv: introduce riscv_cpu_cfg()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 02/11] target/riscv: introduce riscv_cpu_cfg() |
Date: |
Tue, 14 Feb 2023 16:23:47 -0300 |
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..5e4d056772 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
#endif
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
+static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env)
+{
+ return env_archcpu(env)->cfg;
+}
+
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
--
2.39.1
- [PATCH v2 00/11] enable write_misa() and RISCV_FEATURE_* cleanups, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 02/11] target/riscv: introduce riscv_cpu_cfg(),
Daniel Henrique Barboza <=
- [PATCH v2 03/11] target/riscv: allow users to actually write the MISA CSR, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 04/11] target/riscv: remove RISCV_FEATURE_MISA, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 05/11] target/riscv: remove RISCV_FEATURE_DEBUG, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 07/11] target/riscv: remove RISCV_FEATURE_EPMP, Daniel Henrique Barboza, 2023/02/14