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[PATCH v11 2/9] target/riscv: add support for Zca extension
From: |
Weiwei Li |
Subject: |
[PATCH v11 2/9] target/riscv: add support for Zca extension |
Date: |
Thu, 9 Feb 2023 12:13:45 +0800 |
Modify the check for C extension to Zca (C implies Zca)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c | 8 ++++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 4496f21266..ef7c3002b0 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
gen_set_pc(ctx, cpu_pc);
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@@ -178,7 +178,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond
cond)
gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 772f9d7973..1f388ef089 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -569,7 +569,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -1145,7 +1145,11 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
if (insn_len(opcode) == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) {
+ /*
+ * The Zca extension is added as way to refer to instructions in the C
+ * extension that do not include the floating-point loads and stores
+ */
+ if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
return;
}
} else {
--
2.25.1
- [PATCH v11 0/9] support subsets of code size reduction extension, Weiwei Li, 2023/02/08
- [PATCH v11 4/9] target/riscv: add support for Zcd extension, Weiwei Li, 2023/02/08
- [PATCH v11 2/9] target/riscv: add support for Zca extension,
Weiwei Li <=
- [PATCH v11 1/9] target/riscv: add cfg properties for Zc* extension, Weiwei Li, 2023/02/08
- [PATCH v11 3/9] target/riscv: add support for Zcf extension, Weiwei Li, 2023/02/08
- [PATCH v11 6/9] target/riscv: add support for Zcmp extension, Weiwei Li, 2023/02/08
- [PATCH v11 5/9] target/riscv: add support for Zcb extension, Weiwei Li, 2023/02/08
- [PATCH v11 7/9] target/riscv: add support for Zcmt extension, Weiwei Li, 2023/02/08
- [PATCH v11 8/9] target/riscv: expose properties for Zc* extension, Weiwei Li, 2023/02/08
- [PATCH v11 9/9] disas/riscv.c: add disasm support for Zc*, Weiwei Li, 2023/02/08
- Re: [PATCH v11 0/9] support subsets of code size reduction extension, liweiwei, 2023/02/21