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[PATCH v2] target/riscv: fix ctzw behavior
From: |
Vladimir Isaev |
Subject: |
[PATCH v2] target/riscv: fix ctzw behavior |
Date: |
Sat, 4 Feb 2023 11:23:12 +0300 |
According to spec, ctzw should work with 32-bit register, not 64.
For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
v2:
- Use simpler solution suggested by Richard Henderson
---
target/riscv/insn_trans/trans_rvb.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index e2b8329f1e5b..990bc94b9840 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -401,6 +401,7 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
+ ctx->ol = MXL_RV32;
return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
}
--
2.39.1
- [PATCH v2] target/riscv: fix ctzw behavior,
Vladimir Isaev <=