Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented

[Philippe Mathieu-Daudé]

On 17/11/22 18:00, Conor Dooley wrote:
> On Sat, Nov 12, 2022 at 01:34:15PM +0000, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The system controller on PolarFire SoC is access via a mailbox. The
> > control registers for this mailbox lie in the "IOSCB" region & the
> > interrupt is cleared via write to the "SYSREG" region. It also has a
> > QSPI controller, usually connected to a flash chip, that is used for
> > storing FPGA bitstreams and used for In-Application Programming (IAP).
> >
> > Linux has an implementation of the system controller, through which the
> > hwrng is accessed, leading to load/store access faults.
> >
> > Add the QSPI as unimplemented and a very basic (effectively
> > unimplemented) version of the system controller's mailbox. Rather than
> > purely marking the regions as unimplemented, service the mailbox
> > requests by reporting failures and raising the interrupt so a guest can
> > better handle the lack of support.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >   hw/misc/mchp_pfsoc_ioscb.c          | 59 ++++++++++++++++++++++++++++-
> >   hw/misc/mchp_pfsoc_sysreg.c         | 19 ++++++++--
> >   hw/riscv/microchip_pfsoc.c          |  6 +++
> >   include/hw/misc/mchp_pfsoc_ioscb.h  |  3 ++
> >   include/hw/misc/mchp_pfsoc_sysreg.h |  1 +
> >   include/hw/riscv/microchip_pfsoc.h  |  1 +
> >   6 files changed, 83 insertions(+), 6 deletions(-)


> > @@ -143,6 +149,45 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = 
> > {
> >       .endianness = DEVICE_LITTLE_ENDIAN,
> >   };
> >   
> > +#define SERVICES_SR 0x54
> > +
> > +static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
> > +                                     unsigned size)
> > +{
> > +    MchpPfSoCIoscbState *s = opaque;
> > +    uint32_t val = 0;
> > +
> > +    switch (offset) {
> > +    case SERVICES_SR:
> > +        /*
> > +         * Although some services have no error codes, most do. All services
> > +         * that do implement errors, begin their error codes at 1. Treat all
> > +         * service requests as failures & return 1.
> > +         * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
> > +         * user guide for more information on service error codes.
> > +         */
> > +        val = 1;
>
> Another issue I just spotted here, this should not be returning 1, but
> rather 1 << 16. The status bits are 31:16 & I was just getting lucky
> b/c of something wrong with the Linux driver exercising it!

So your implementation expects 32-bit accesses, thus ...

> > +        qemu_irq_raise(s->irq);
> > +        break;
> > +    default:
> > +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> > +                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> > +                      __func__, size, offset);
> > +    }
> > +
> > +    return val;
> > +}
> > +
> > +/*
> > + * use the dummy write, since we are always going to report a failed message
> > + * and therefore do not care what service is actually requested
> > + */
> > +static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
> > +    .read = mchp_pfsoc_ctrl_read,
> > +    .write = mchp_pfsoc_dummy_write,
> > +    .endianness = DEVICE_LITTLE_ENDIAN,

... you might want to complete this with (at least):

        .impl.min_access_size = 4,

And eventually if this region is only accessible as 32-bit:

        .valid.min_access_size = 4,

> > +};