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[PATCH v2 0/8] support subsets of code size reduction extension
From: |
Weiwei Li |
Subject: |
[PATCH v2 0/8] support subsets of code size reduction extension |
Date: |
Sun, 13 Nov 2022 10:32:43 +0800 |
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version
instructions.
Specification:
https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v2
To test Zc* implementation, specify cpu argument with
'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or
"x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or
Zcmp,Zcmt) extension support.
This implementation can pass the basic zc tests from
https://github.com/yulong-plct/zc-test
v2:
* add check for relationship between Zca/Zcf/Zcd with C/F/D based on related
discussion in review of Zc* spec
* separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt
Weiwei Li (8):
target/riscv: add cfg properties for Zc* extension
target/riscv: add support for Zca and Zcf extensions
target/riscv: add support for Zcd extension
target/riscv: add support for Zcb extension
target/riscv: add support for Zcmp extension
target/riscv: add support for Zcmt extension
target/riscv: expose properties for Zc* extension
disas/riscv.c: add disasm support for Zc*
disas/riscv.c | 287 +++++++++++++++++++++-
target/riscv/cpu.c | 56 +++++
target/riscv/cpu.h | 8 +
target/riscv/cpu_bits.h | 7 +
target/riscv/csr.c | 35 +++
target/riscv/helper.h | 7 +
target/riscv/insn16.decode | 52 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++
target/riscv/insn_trans/trans_rvf.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 4 +-
target/riscv/insn_trans/trans_rvzce.c.inc | 265 ++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 6 +-
target/riscv/machine.c | 19 ++
target/riscv/meson.build | 3 +-
target/riscv/translate.c | 23 +-
target/riscv/zce_helper.c | 244 ++++++++++++++++++
16 files changed, 1025 insertions(+), 17 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc
create mode 100644 target/riscv/zce_helper.c
--
2.25.1
- [PATCH v2 0/8] support subsets of code size reduction extension,
Weiwei Li <=
- [PATCH v2 3/8] target/riscv: add support for Zcd extension, Weiwei Li, 2022/11/12
- [PATCH v2 1/8] target/riscv: add cfg properties for Zc* extension, Weiwei Li, 2022/11/12
- [PATCH v2 4/8] target/riscv: add support for Zcb extension, Weiwei Li, 2022/11/12
- [PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions, Weiwei Li, 2022/11/12
- [PATCH v2 5/8] target/riscv: add support for Zcmp extension, Weiwei Li, 2022/11/12