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[PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger
From: |
Bin Meng |
Subject: |
[PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger |
Date: |
Fri, 9 Sep 2022 21:42:14 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
target/riscv/debug.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 7a8910f980..e16d5c070a 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -464,6 +464,11 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
pc = env->tdata2[i];
@@ -499,6 +504,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
addr = env->tdata2[i];
flags = 0;
--
2.34.1
- [PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, (continued)
- [PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, Bin Meng, 2022/09/09
- [PATCH v2 3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, Bin Meng, 2022/09/09
- [PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written, Bin Meng, 2022/09/09
- [PATCH v2 5/8] target/riscv: debug: Introduce tinfo CSR, Bin Meng, 2022/09/09
- [PATCH v2 6/8] target/riscv: debug: Create common trigger actions function, Bin Meng, 2022/09/09
- [PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger,
Bin Meng <=
- [PATCH v2 8/8] target/riscv: debug: Add initial support of type 6 trigger, Bin Meng, 2022/09/09
- Re: [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support, Alistair Francis, 2022/09/23