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[PATCH 1/2] target/riscv: Remove CSRs that set/clear an IMSIC interrupt
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From: |
Anup Patel |
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Subject: |
[PATCH 1/2] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits |
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Date: |
Thu, 16 Jun 2022 08:45:42 +0530 |
Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
These CSRs were mostly for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.
We update the IMSIC CSR emulation as-per above to match the latest AIA
draft specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
target/riscv/cpu_bits.h | 24 +------
target/riscv/csr.c | 150 +---------------------------------------
2 files changed, 6 insertions(+), 168 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4a55c6a709..01608f86e5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -177,14 +177,8 @@
#define CSR_MIREG 0x351
/* Machine-Level Interrupts (AIA) */
-#define CSR_MTOPI 0xfb0
-
-/* Machine-Level IMSIC Interface (AIA) */
-#define CSR_MSETEIPNUM 0x358
-#define CSR_MCLREIPNUM 0x359
-#define CSR_MSETEIENUM 0x35a
-#define CSR_MCLREIENUM 0x35b
#define CSR_MTOPEI 0x35c
+#define CSR_MTOPI 0xfb0
/* Virtual Interrupts for Supervisor Level (AIA) */
#define CSR_MVIEN 0x308
@@ -224,14 +218,8 @@
#define CSR_SIREG 0x151
/* Supervisor-Level Interrupts (AIA) */
-#define CSR_STOPI 0xdb0
-
-/* Supervisor-Level IMSIC Interface (AIA) */
-#define CSR_SSETEIPNUM 0x158
-#define CSR_SCLREIPNUM 0x159
-#define CSR_SSETEIENUM 0x15a
-#define CSR_SCLREIENUM 0x15b
#define CSR_STOPEI 0x15c
+#define CSR_STOPI 0xdb0
/* Supervisor-Level High-Half CSRs (AIA) */
#define CSR_SIEH 0x114
@@ -282,14 +270,8 @@
#define CSR_VSIREG 0x251
/* VS-Level Interrupts (H-extension with AIA) */
-#define CSR_VSTOPI 0xeb0
-
-/* VS-Level IMSIC Interface (H-extension with AIA) */
-#define CSR_VSSETEIPNUM 0x258
-#define CSR_VSCLREIPNUM 0x259
-#define CSR_VSSETEIENUM 0x25a
-#define CSR_VSCLREIENUM 0x25b
#define CSR_VSTOPEI 0x25c
+#define CSR_VSTOPI 0xeb0
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
#define CSR_HIDELEGH 0x613
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 409a209f14..a4890ebc70 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1040,14 +1040,6 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int
csrno)
return CSR_VSISELECT;
case CSR_SIREG:
return CSR_VSIREG;
- case CSR_SSETEIPNUM:
- return CSR_VSSETEIPNUM;
- case CSR_SCLREIPNUM:
- return CSR_VSCLREIPNUM;
- case CSR_SSETEIENUM:
- return CSR_VSSETEIENUM;
- case CSR_SCLREIENUM:
- return CSR_VSCLREIENUM;
case CSR_STOPEI:
return CSR_VSTOPEI;
default:
@@ -1202,124 +1194,6 @@ done:
return RISCV_EXCP_NONE;
}
-static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
- target_ulong new_val, target_ulong wr_mask)
-{
- int ret = -EINVAL;
- bool set, pend, virt;
- target_ulong priv, isel, vgein, xlen, nval, wmask;
-
- /* Translate CSR number for VS-mode */
- csrno = aia_xlate_vs_csrno(env, csrno);
-
- /* Decode register details from CSR number */
- virt = set = pend = false;
- switch (csrno) {
- case CSR_MSETEIPNUM:
- priv = PRV_M;
- set = true;
- pend = true;
- break;
- case CSR_MCLREIPNUM:
- priv = PRV_M;
- pend = true;
- break;
- case CSR_MSETEIENUM:
- priv = PRV_M;
- set = true;
- break;
- case CSR_MCLREIENUM:
- priv = PRV_M;
- break;
- case CSR_SSETEIPNUM:
- priv = PRV_S;
- set = true;
- pend = true;
- break;
- case CSR_SCLREIPNUM:
- priv = PRV_S;
- pend = true;
- break;
- case CSR_SSETEIENUM:
- priv = PRV_S;
- set = true;
- break;
- case CSR_SCLREIENUM:
- priv = PRV_S;
- break;
- case CSR_VSSETEIPNUM:
- priv = PRV_S;
- virt = true;
- set = true;
- pend = true;
- break;
- case CSR_VSCLREIPNUM:
- priv = PRV_S;
- virt = true;
- pend = true;
- break;
- case CSR_VSSETEIENUM:
- priv = PRV_S;
- virt = true;
- set = true;
- break;
- case CSR_VSCLREIENUM:
- priv = PRV_S;
- virt = true;
- break;
- default:
- goto done;
- };
-
- /* IMSIC CSRs only available when machine implements IMSIC. */
- if (!env->aia_ireg_rmw_fn[priv]) {
- goto done;
- }
-
- /* Find the selected guest interrupt file */
- vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
-
- /* Selected guest interrupt file should be valid */
- if (virt && (!vgein || env->geilen < vgein)) {
- goto done;
- }
-
- /* Set/Clear CSRs always read zero */
- if (val) {
- *val = 0;
- }
-
- if (wr_mask) {
- /* Get interrupt number */
- new_val &= wr_mask;
-
- /* Find target interrupt pending/enable register */
- xlen = riscv_cpu_mxl_bits(env);
- isel = (new_val / xlen);
- isel *= (xlen / IMSIC_EIPx_BITS);
- isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
-
- /* Find the interrupt bit to be set/clear */
- wmask = ((target_ulong)1) << (new_val % xlen);
- nval = (set) ? wmask : 0;
-
- /* Call machine specific IMSIC register emulation */
- ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
- AIA_MAKE_IREG(isel, priv, virt,
- vgein, xlen),
- NULL, nval, wmask);
- } else {
- ret = 0;
- }
-
-done:
- if (ret) {
- return (riscv_cpu_virt_enabled(env) && virt) ?
- RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
- }
- return RISCV_EXCP_NONE;
-}
-
static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
@@ -3409,14 +3283,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
/* Machine-Level Interrupts (AIA) */
- [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
-
- /* Machine-Level IMSIC Interface (AIA) */
- [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
- [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
- [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
- [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
[CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
+ [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
/* Virtual Interrupts for Supervisor Level (AIA) */
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
@@ -3464,14 +3332,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
/* Supervisor-Level Interrupts (AIA) */
- [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
-
- /* Supervisor-Level IMSIC Interface (AIA) */
- [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum
},
- [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum
},
- [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum
},
- [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum
},
[CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
+ [CSR_STOPI] = { "stopi", aia_smode, read_stopi },
/* Supervisor-Level High-Half CSRs (AIA) */
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
@@ -3543,14 +3405,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg
},
/* VS-Level Interrupts (H-extension with AIA) */
- [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
-
- /* VS-Level IMSIC Interface (H-extension with AIA) */
- [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL,
rmw_xsetclreinum },
- [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL,
rmw_xsetclreinum },
- [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL,
rmw_xsetclreinum },
- [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL,
rmw_xsetclreinum },
[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
+ [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh
},
--
2.34.1