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Re: [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR
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From: |
Bin Meng |
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Subject: |
Re: [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR |
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Date: |
Wed, 15 Jun 2022 20:26:45 +0800 |
On Fri, Jun 10, 2022 at 1:21 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> tinfo.info:
> One bit for each possible type enumerated in tdata1.
> If the bit is set, then that type is supported by the currently
> selected trigger.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu_bits.h | 1 +
> target/riscv/csr.c | 8 ++++++++
> target/riscv/debug.c | 10 +++++++---
> target/riscv/debug.h | 2 ++
> 4 files changed, 18 insertions(+), 3 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, (continued)
- [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, frank . chang, 2022/06/10
- [PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type, frank . chang, 2022/06/10
- [PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers, frank . chang, 2022/06/10
- [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, frank . chang, 2022/06/10
- [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR, frank . chang, 2022/06/10
- Re: [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR,
Bin Meng <=
- [PATCH 6/9] target/riscv: debug: Create common trigger actions function, frank . chang, 2022/06/10
- [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger, frank . chang, 2022/06/10
- [PATCH 9/9] target/riscv: debug: Add initial support of type 6 trigger, frank . chang, 2022/06/10