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[PATCH qemu v12 13/15] target/riscv: rvv: Add tail agnostic for vector m
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From: |
~eopxd |
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Subject: |
[PATCH qemu v12 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions |
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Date: |
Thu, 28 Apr 2022 06:40:06 -0000 |
From: eopXD <eop.chen@sifive.com>
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++++
target/riscv/vector_helper.c | 30 +++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index a267945267..ab9f876c28 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3209,6 +3209,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a)
\
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = \
+ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -3313,6 +3315,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = \
+ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, s->cfg_ptr->vlen / 8, \
@@ -3350,6 +3354,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -3379,6 +3384,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e0fd0e62b3..9a663a406d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4697,6 +4697,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
int a, b; \
\
@@ -4706,6 +4708,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail- \
+ * agnostic \
+ */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
#define DO_NAND(N, M) (!(N & M))
@@ -4773,6 +4784,8 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen;
+ uint32_t vta_all_1s = vext_vta_all_1s(desc);
int i;
bool first_mask_bit = false;
@@ -4801,6 +4814,13 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
}
}
env->vstart = 0;
+ /* mask destination register are always tail-agnostic */
+ /* set tail elements to 1s */
+ if (vta_all_1s) {
+ for (; i < total_elems; i++) {
+ vext_set_elem_mask(vd, i, 1);
+ }
+ }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
@@ -4828,6 +4848,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
CPURISCVState *env, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t sum = 0; \
int i; \
\
@@ -4841,6 +4864,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
CPURISCVState *env, \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1)
@@ -4854,6 +4879,9 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env,
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
int i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -4863,6 +4891,8 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env,
uint32_t desc) \
*((ETYPE *)vd + H(i)) = i; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1)
--
2.34.2
- [PATCH qemu v12 04/15] target/riscv: rvv: Add tail agnostic for vv instructions, (continued)
- [PATCH qemu v12 04/15] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 06/15] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 05/15] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 10/15] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 08/15] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 01/15] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/04/28
- [PATCH qemu v12 09/15] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 14/15] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/04/28
- [PATCH qemu v12 13/15] target/riscv: rvv: Add tail agnostic for vector mask instructions,
~eopxd <=
- [PATCH qemu v12 15/15] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior, ~eopxd, 2022/04/28
- [PATCH qemu v12 11/15] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/04/28