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[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permuta
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From: |
~eopxd |
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Subject: |
[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions |
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Date: |
Mon, 25 Apr 2022 14:18:47 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 34 +++++++++++++++++++++++--
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 69d00c7116..3858a0479a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3975,6 +3975,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a,
uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 600ccad513..e87806ed64 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5037,11 +5037,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
target_ulong offset = s1, i_min, i; \
\
i_min = MAX(env->vstart, offset); \
for (i = i_min; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -5067,13 +5071,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
target_ulong i_max, i; \
\
i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
for (i = env->vstart; i < i_max; ++i) { \
- if (vm || vext_elem_mask(v0, i)) { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
+ continue; \
} \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
} \
\
for (i = i_max; i < vl; ++i) { \
@@ -5104,10 +5113,14 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
if (i == 0) { \
@@ -5150,10 +5163,14 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
if (i == vl - 1) { \
@@ -5222,11 +5239,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t esz = sizeof(TS2); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint64_t index; \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
index = *((TS1 *)vs1 + HS1(i)); \
@@ -5263,11 +5284,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint64_t index = s1; \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
if (index >= vlmax) { \
@@ -5349,10 +5374,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
\
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, \
+ i * esz, \
+ (i + 1) * esz); \
continue; \
} \
*((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
--
2.34.2
- [PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/04/25
- [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/04/25
- [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/04/25
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/04/25
[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions,
~eopxd <=
[PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/04/25
[PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/04/25
[PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/04/25
[PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/04/25
[PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/04/25