Re: [PATCH v11 00/14] support subsets of scalar crypto extension

[Alistair Francis]

On Tue, Apr 19, 2022 at 11:58 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements RISC-V scalar crypto extension v1.0.0 version 
> instructions.
> Partial instructions are reused from B-extension.
>
> Specification:
> https://github.com/riscv/riscv-crypto
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v11
>
> To test rvk implementation, specify cpu argument with 'zks=true,zkn=true' or 
> "zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true"
>  to enable K-extension support. This implementation can pass the ACT tests 
> for K with our extended act support for qemu (available at 
> https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v11-with-act)
>
> Review status:
> patch 5 is reviewed by Philippe Mathieu-Daudé
> patch 1~11 and 13-14 are acked or reviewed by Alistair Francis
> patch 2~11 are reviewed by Richard Henderson (fix new comments on patch 6 and 
> 7)
>
> v11:
> * patch 6: add REQUIRE_32BIT to trans_* function for aes RV32 instruction
> * patch 7: add REQUIRE_64BIT to trans_* function for aes RV64 instruction
>
> v10:
> (only patch 12 is modified)
> * simplify the conditions for the check in seed function
> * add NULL check for ret_val in rmw_seed function
> * remain the change of MSECCFG_* to align with the added MSECCFG_*SEED
>
> v9:
> * check whether seed is accessed by a read-write instruction in helper_csrr.
> * fix disas for partial scalar crypto instructions
> * rebase on 
> https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00156.html
>
> v8:
> * replace large macro for trans function of sha256/512 instructions with 
> parameters to gen_sha* function in patch 8,9,10
> * fix tcg_const_tl to tcg_constant_tl
> * fix rmw_seed function
>
> v7:
> * reuse gen_unary/gen_arith to simplify trans_* functions
> * replace DEF_HELPER_* with DEF_HEPER_FLAG_*
> * move aes64 related macros from patch 6 to patch 7
> * create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
> * replace bs with shamt (bs << 3)
> * optimize trans function for sha256, sha512 and sm4 instructions to be 
> generated inline
>
> v6:
> * add reviewed-by tags
> * rebase on upstream
>
> v5:
> * split the big patches
>
> v4:
> * drop "x-" in exposed properties
> * delete unrelated changes
>
> v3:
> * add extension check for SEED csr access
>
> v2:
> * optimize implementation for brev8, xperm, zip, unzip
> * use aes related sbox array from crypto/aes.h
> * move sm4_sbox to crypto/sm4.c, and share it with target/arm
>
> Weiwei Li (14):
>   target/riscv: rvk: add cfg properties for zbk* and zk*
>   target/riscv: rvk: add support for zbkb extension
>   target/riscv: rvk: add support for zbkc extension
>   target/riscv: rvk: add support for zbkx extension
>   crypto: move sm4_sbox from target/arm
>   target/riscv: rvk: add support for zknd/zkne extension in RV32
>   target/riscv: rvk: add support for zkne/zknd extension in RV64
>   target/riscv: rvk: add support for sha256 related instructions in zknh
>     extension
>   target/riscv: rvk: add support for sha512 related instructions for
>     RV32 in zknh extension
>   target/riscv: rvk: add support for sha512 related instructions for
>     RV64 in zknh extension
>   target/riscv: rvk: add support for zksed/zksh extension
>   target/riscv: rvk: add CSR support for Zkr
>   disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>   target/riscv: rvk: expose zbk* and zk* properties

Do you mind rebasing this on the latest master? Then I can merge it

Alistair

>
>  crypto/meson.build                      |   1 +
>  crypto/sm4.c                            |  49 +++
>  disas/riscv.c                           | 173 ++++++++++-
>  include/crypto/sm4.h                    |   6 +
>  target/arm/crypto_helper.c              |  36 +--
>  target/riscv/bitmanip_helper.c          |  80 +++++
>  target/riscv/cpu.c                      |  36 +++
>  target/riscv/cpu.h                      |  13 +
>  target/riscv/cpu_bits.h                 |   9 +
>  target/riscv/crypto_helper.c            | 302 ++++++++++++++++++
>  target/riscv/csr.c                      |  80 +++++
>  target/riscv/helper.h                   |  22 ++
>  target/riscv/insn32.decode              |  97 ++++--
>  target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++-
>  target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++
>  target/riscv/meson.build                |   3 +-
>  target/riscv/op_helper.c                |   9 +
>  target/riscv/pmp.h                      |   8 +-
>  target/riscv/translate.c                |   8 +
>  19 files changed, 1368 insertions(+), 71 deletions(-)
>  create mode 100644 crypto/sm4.c
>  create mode 100644 include/crypto/sm4.h
>  create mode 100644 target/riscv/crypto_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
>
> --
> 2.17.1
>
>