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[PATCH v5 5/6] target/riscv: cpu: Enable native debug feature
From: |
Bin Meng |
Subject: |
[PATCH v5 5/6] target/riscv: cpu: Enable native debug feature |
Date: |
Thu, 21 Apr 2022 08:33:23 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 85656cdcc3..0c774056c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
- DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
- [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Bin Meng, 2022/04/20
- [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/04/20
- [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2022/04/20
- [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/04/20
- [PATCH v5 4/6] target/riscv: machine: Add debug state description, Bin Meng, 2022/04/20
- [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature,
Bin Meng <=
- [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2022/04/20
- Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/04/20