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[PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu
From: |
Atish Patra |
Subject: |
[PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu |
Date: |
Wed, 30 Mar 2022 17:01:17 -0700 |
From: Atish Patra <atish.patra@wdc.com>
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 86e48ff54dd1..1995ed0d6979 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -794,7 +794,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d351b0ce12bf..92bad7e35e4d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -378,7 +378,7 @@ struct RISCVCPUConfig {
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
bool ext_svinval;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 914b3f96ef67..f1b264b2c7a4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -72,8 +72,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.ext_pmu) {
+ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
- [PATCH v7 00/12] Improve PMU support, Atish Patra, 2022/03/30
- [PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/03/30
- [PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu,
Atish Patra <=
- [PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/03/30
- [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/03/30
- [PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/03/30
- [PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/03/30
- [PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/03/30
- [PATCH v7 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/03/30
- [PATCH v7 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/03/30
- [PATCH v7 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/03/30
- [PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2022/03/30
- [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/03/30