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[PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector in
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From: |
~eopxd |
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Subject: |
[PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions |
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Date: |
Thu, 24 Mar 2022 19:03:51 -0000 |
From: eopXD <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 28 +++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index ccbc55a2ab..24784b6f5f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2113,11 +2113,21 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v
*a)
/* vmv.v.v has rs2 = 0 and vm = 1 */
vext_check_sss(s, a->rd, a->rs1, 0, 1)) {
if (s->vl_eq_vlmax) {
+ if (s->vta && s->lmul < 0) {
+ /* tail elements may pass vlmax when lmul < 0
+ * set tail elements to 1s
+ */
+ uint32_t vlenb = s->cfg_ptr->vlen >> 3;
+ tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rd), -1,
+ vlenb, vlenb);
+ }
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
vreg_ofs(s, a->rs1),
MAXSZ(s), MAXSZ(s));
} else {
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -2153,6 +2163,15 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x
*a)
s1 = get_gpr(s, a->rs1, EXT_SIGN);
if (s->vl_eq_vlmax) {
+ if (s->vta && s->lmul < 0) {
+ /* tail elements may pass vlmax when lmul < 0
+ * set tail elements to 1s
+ */
+ uint32_t vlenb = s->cfg_ptr->vlen >> 3;
+ tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rd), -1,
+ vlenb, vlenb);
+ }
tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), s1);
} else {
@@ -2160,6 +2179,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
TCGv_i64 s1_i64 = tcg_temp_new_i64();
TCGv_ptr dest = tcg_temp_new_ptr();
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -2190,6 +2210,15 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i
*a)
vext_check_ss(s, a->rd, 0, 1)) {
int64_t simm = sextract64(a->rs1, 0, 5);
if (s->vl_eq_vlmax) {
+ if (s->vta && s->lmul < 0) {
+ /* tail elements may pass vlmax when lmul < 0
+ * set tail elements to 1s
+ */
+ uint32_t vlenb = s->cfg_ptr->vlen >> 3;
+ tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rd), -1,
+ vlenb, vlenb);
+ }
tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), simm);
mark_vs_dirty(s);
@@ -2198,6 +2227,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
TCGv_i64 s1;
TCGv_ptr dest;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -2770,6 +2800,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
TCGv_i64 t1;
if (s->vl_eq_vlmax) {
+ if (s->vta && s->lmul < 0) {
+ /* tail elements may pass vlmax when lmul < 0
+ * set tail elements to 1s
+ */
+ uint32_t vlenb = s->cfg_ptr->vlen >> 3;
+ tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rd), -1,
+ vlenb, vlenb);
+ }
t1 = tcg_temp_new_i64();
/* NaN-box f[rs1] */
do_nanbox(s, t1, cpu_fpr[a->rs1]);
@@ -2781,6 +2820,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
TCGv_ptr dest;
TCGv_i32 desc;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_vmv_vx * const fns[3] = {
gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a972946bc2..89927a424f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1964,6 +1964,10 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState
*env, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env_archcpu(env), \
+ env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1971,6 +1975,9 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState
*env, \
*((ETYPE *)vd + H(i)) = s1; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1)
@@ -1983,12 +1990,19 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState
*env, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env_archcpu(env), \
+ env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
*((ETYPE *)vd + H(i)) = (ETYPE)s1; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1)
@@ -2001,6 +2015,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env_archcpu(env), \
+ env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -2008,6 +2026,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1)
@@ -2020,6 +2041,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env_archcpu(env), \
+ env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -2029,6 +2054,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
\
*((ETYPE *)vd + H(i)) = d; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ total_elems * esz); \
}
GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1)
--
2.34.1
- [PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, (continued)
- [PATCH qemu v4 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 03/14] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/03/24
- [PATCH qemu v4 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, ~eopxd, 2022/03/24
- [PATCH qemu v4 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions,
~eopxd <=
- [PATCH qemu v4 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/03/24
- [PATCH qemu v4 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/03/24