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[PATCH qemu v3 14/14] target/riscv: rvv: Add tail agnostic for vector pe
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From: |
~eopxd |
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Subject: |
[PATCH qemu v3 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions |
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Date: |
Wed, 23 Mar 2022 03:58:36 -0000 |
From: eopXD <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +
target/riscv/vector_helper.c | 54 ++++++++++++++++++++++---
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index cce811f67f..92ee0641ba 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3739,6 +3739,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, s->cfg_ptr->vlen / 8,
@@ -3844,6 +3845,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a,
uint8_t seq)
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8ebd26be93..595cfa3e0e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4932,6 +4932,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
target_ulong offset = s1, i_min, i; \
\
i_min = MAX(env->vstart, offset); \
@@ -4941,6 +4944,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
@@ -4953,12 +4958,15 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
+ uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
target_ulong i_max, i; \
\
- i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
+ i_max = MAX(MIN(s1 < max_elem ? max_elem - s1 : 0, vl), env->vstart); \
for (i = env->vstart; i < i_max; ++i) { \
if (vm || vext_elem_mask(v0, i)) { \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
@@ -4972,6 +4980,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
} \
\
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -4987,6 +4997,9 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -5000,6 +5013,8 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VSLIE1UP(8, H1)
@@ -5027,6 +5042,9 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
typedef uint##BITWIDTH##_t ETYPE; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -5040,6 +5058,8 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0,
target_ulong s1, \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
GEN_VEXT_VSLIDE1DOWN(8, H1)
@@ -5090,9 +5110,12 @@ GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \
+ uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(TS2))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(TS2); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint64_t index; \
uint32_t i; \
\
@@ -5101,13 +5124,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
continue; \
} \
index = *((TS1 *)vs1 + HS1(i)); \
- if (index >= vlmax) { \
+ if (index >= max_elem) { \
*((TS2 *)vd + HS2(i)) = 0; \
} else { \
*((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -5125,9 +5150,12 @@ GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t,
uint64_t, H2, H8)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
+ uint32_t max_elem = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint64_t index = s1; \
uint32_t i; \
\
@@ -5135,13 +5163,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- if (index >= vlmax) { \
+ if (index >= max_elem) { \
*((ETYPE *)vd + H(i)) = 0; \
} else { \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -5156,6 +5186,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t num = 0, i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -5166,6 +5199,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
num++; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, vlmax * esz); \
}
/* Compress into vd elements of vs2 where vs1 is enabled */
@@ -5202,6 +5237,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
\
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc); \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t vlmax = \
+ vext_get_total_elem(env_archcpu(env), env->vtype); \
+ uint32_t vta = vext_vta(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -5211,6 +5250,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
\
*((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vta, vl, vl * esz, \
+ vlmax * esz); \
}
GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1)
--
2.34.1
- [PATCH qemu v3 04/14] target/riscv: rvv: Add tail agnostic for vv instructions, (continued)
- [PATCH qemu v3 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 02/14] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/03/22
- [PATCH qemu v3 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions,
~eopxd <=
- [PATCH qemu v3 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/03/22
- [PATCH qemu v3 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions, ~eopxd, 2022/03/22
- Re: [PATCH qemu v3 00/14] Add tail agnostic behavior for rvv instructions, Weiwei Li, 2022/03/23