qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function


From: Alistair Francis
Subject: Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function
Date: Thu, 3 Mar 2022 15:22:26 +1000

On Sat, Feb 19, 2022 at 10:34 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  target/riscv/csr.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b16881615997..3799ee850087 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -94,8 +94,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>              }
>              break;
>          case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> -            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) 
> &&
> -                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> +            ctr_index = csrno - CSR_CYCLE;
> +            if (!get_field(env->hcounteren, 1 << ctr_index) &&
> +                 get_field(env->mcounteren, 1 << ctr_index)) {

This fails to build:

../target/riscv/csr.c: In function ‘ctr’:
../target/riscv/csr.c:99:13: error: ‘ctr_index’ undeclared (first use
in this function); did you mean ‘tlb_index’?
  99 |             ctr_index = csrno - CSR_CYCLE;
     |             ^~~~~~~~~
     |             tlb_index

Alistair

>                  return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>              }
>              break;
> @@ -121,8 +122,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>                  }
>                  break;
>              case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> -                if (!get_field(env->hcounteren, 1 << (csrno - 
> CSR_HPMCOUNTER3H)) &&
> -                    get_field(env->mcounteren, 1 << (csrno - 
> CSR_HPMCOUNTER3H))) {
> +                ctr_index = csrno - CSR_CYCLEH;
> +                if (!get_field(env->hcounteren, 1 << ctr_index) &&
> +                     get_field(env->mcounteren, 1 << ctr_index)) {
>                      return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>                  }
>                  break;
> --
> 2.30.2
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]