[PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension

[Weiwei Li]

 - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and 
sha512sig1h instructions

Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn32.decode              |  6 +++
 target/riscv/insn_trans/trans_rvk.c.inc | 63 +++++++++++++++++++++++++
 2 files changed, 69 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index db28ecdd2b..02a0c71890 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -862,3 +862,9 @@ sha256sig0  00 01000 00010 ..... 001 ..... 0010011 @r2
 sha256sig1  00 01000 00011 ..... 001 ..... 0010011 @r2
 sha256sum0  00 01000 00000 ..... 001 ..... 0010011 @r2
 sha256sum1  00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc 
b/target/riscv/insn_trans/trans_rvk.c.inc
index 02a3261675..f1dccc13c8 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -149,3 +149,66 @@ GEN_SHA256(sha256sig0, shri, 7, 18, 3)
 GEN_SHA256(sha256sig1, shri, 17, 19, 10)
 GEN_SHA256(sha256sum0, rotri, 2, 13, 22)
 GEN_SHA256(sha256sum1, rotri, 6, 11, 25)
+
+#define GEN_SHA512_RV32(NAME, OP1, NUM1, OP2, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+    TCGv_i64 t0 = tcg_temp_new_i64(); \
+    TCGv_i64 t1 = tcg_temp_new_i64(); \
+    TCGv_i64 t2 = tcg_temp_new_i64(); \
+    \
+    tcg_gen_concat_tl_i64(t0, src1, src2); \
+    tcg_gen_##OP1##_i64(t1, t0, NUM1); \
+    tcg_gen_##OP2##_i64(t2, t0, NUM2); \
+    tcg_gen_xor_i64(t1, t1, t2); \
+    tcg_gen_rotri_i64(t2, t0, NUM3); \
+    tcg_gen_xor_i64(t1, t1, t2); \
+    tcg_gen_trunc_i64_tl(dest, t1); \
+    \
+    tcg_temp_free_i64(t0); \
+    tcg_temp_free_i64(t1); \
+    tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+    REQUIRE_32BIT(ctx); \
+    REQUIRE_ZKNH(ctx); \
+    return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512_RV32(sha512sum0r, rotli, 25, rotli, 30, 28)
+GEN_SHA512_RV32(sha512sum1r, rotli, 23, rotri, 14, 18)
+GEN_SHA512_RV32(sha512sig0l, rotri, 1, rotri, 7, 8)
+GEN_SHA512_RV32(sha512sig1l, rotli, 3, rotri, 6, 19)
+
+#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+    TCGv_i64 t0 = tcg_temp_new_i64(); \
+    TCGv_i64 t1 = tcg_temp_new_i64(); \
+    TCGv_i64 t2 = tcg_temp_new_i64(); \
+    \
+    tcg_gen_concat_tl_i64(t0, src1, src2); \
+    tcg_gen_##OP##_i64(t1, t0, NUM1); \
+    tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
+    tcg_gen_shri_i64(t2, t2, NUM2); \
+    tcg_gen_xor_i64(t1, t1, t2); \
+    tcg_gen_rotri_i64(t2, t0, NUM3); \
+    tcg_gen_xor_i64(t1, t1, t2); \
+    tcg_gen_trunc_i64_tl(dest, t1); \
+    \
+    tcg_temp_free_i64(t0); \
+    tcg_temp_free_i64(t1); \
+    tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+    REQUIRE_32BIT(ctx); \
+    REQUIRE_ZKNH(ctx); \
+    return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8)
+GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)
-- 
2.17.1