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[RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix
From: |
Tsukasa OI |
Subject: |
[RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix |
Date: |
Sat, 12 Feb 2022 20:59:09 +0900 |
S and U are misa bits but not extensions. Thus, they should not be
copied to the ISA string.
I am truly surprised that this patchset is the THIRD attempt to fix this
longstanding problem.
(1) August 2019: by Palmer Dabbelt
<https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00165.html>
<https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00141.html>
<https://lists.nongnu.org/archive/html/qemu-riscv/2019-08/msg00259.html>
(2) April 2021: by Emmanuel Blot
<https://lists.nongnu.org/archive/html/qemu-riscv/2021-04/msg00248.html>
(3) February 2022: by me (this patchset)
I feel this is urgent to eliminate this bug now considering it required
a workaround to RISC-V Linux kernel as I pointed out:
<http://lists.infradead.org/pipermail/linux-riscv/2022-February/012252.html>
Though my patchset is first developed independently, this submitted
version is influenced by (2) Emmanuel Blot's patchset. Thanks to this,
constant "[n]" can now be variable "[]".
It also fixes an ordering issue where 'C' should be preceded by 'L'
(order: 'L' -> 'C') as per the RISC-V ISA Manual (version 20191213),
Table 27.1.
It clarifies the role of `riscv_exts'. It's a single-letter extrension
ordering list.
Tsukasa OI (1):
target/riscv: misa to ISA string conversion fix
target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
base-commit: 0a301624c2f4ced3331ffd5bce85b4274fe132af
--
2.32.0
- [RESEND PATCH 0/1] target/riscv: misa to ISA string conversion fix,
Tsukasa OI <=