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[PATCH 0/2] RISC-V: Correctly generate store/amo faults
From: |
Alistair Francis |
Subject: |
[PATCH 0/2] RISC-V: Correctly generate store/amo faults |
Date: |
Mon, 24 Jan 2022 10:59:56 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
This fixes: https://gitlab.com/qemu-project/qemu/-/issues/594
Alistair Francis (2):
accel: tcg: Allow forcing a store fault on read ops
targett/riscv: rva: Correctly generate a store/amo fault
include/exec/memop.h | 2 +
accel/tcg/cputlb.c | 11 ++++-
target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++---------
3 files changed, 48 insertions(+), 21 deletions(-)
--
2.31.1
- [PATCH 0/2] RISC-V: Correctly generate store/amo faults,
Alistair Francis <=