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[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops
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From: |
Atish Patra |
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Subject: |
[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops. |
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Date: |
Thu, 20 Jan 2022 12:07:32 -0800 |
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++---------------
2 files changed, 69 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 671f65100b1a..7f87917204c5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -521,6 +521,7 @@ typedef struct {
riscv_csr_op_fn op;
riscv_csr_read128_fn read128;
riscv_csr_write128_fn write128;
+ uint32_t min_priv_ver;
} riscv_csr_operations;
/* CSR function table constants */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d1f..762d3269b4a4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1991,13 +1991,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { "frm", fs, read_frm, write_frm },
[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
/* Vector CSRs */
- [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
- [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
- [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
- [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
- [CSR_VL] = { "vl", vs, read_vl },
- [CSR_VTYPE] = { "vtype", vs, read_vtype },
- [CSR_VLENB] = { "vlenb", vs, read_vlenb },
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, NULL,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, NULL,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, NULL,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, NULL,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_VL] = { "vl", vs, read_vl, NULL, NULL, NULL, NULL,
+ PRIV_VERSION_1_12_0 },
+ [CSR_VTYPE] = { "vtype", vs, read_vtype, NULL, NULL, NULL, NULL,
+ PRIV_VERSION_1_12_0 },
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb, NULL, NULL, NULL, NULL,
+ PRIV_VERSION_1_12_0 },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_instret },
[CSR_INSTRET] = { "instret", ctr, read_instret },
@@ -2063,36 +2070,62 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor Protection and Translation */
[CSR_SATP] = { "satp", smode, read_satp, write_satp },
- [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
write_hstatus },
- [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
write_hedeleg },
- [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg,
write_hideleg },
- [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip
},
- [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip
},
- [CSR_HIE] = { "hie", hmode, read_hie, write_hie
},
- [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
write_hcounteren },
- [CSR_HGEIE] = { "hgeie", hmode, read_zero,
write_hgeie },
- [CSR_HTVAL] = { "htval", hmode, read_htval,
write_htval },
- [CSR_HTINST] = { "htinst", hmode, read_htinst,
write_htinst },
- [CSR_HGEIP] = { "hgeip", hmode, read_zero,
write_hgeip },
- [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
write_hgatp },
- [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta },
- [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
write_htimedeltah },
-
- [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
write_vsstatus },
- [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip
},
- [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie
},
- [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
write_vstvec },
- [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
write_vsscratch },
- [CSR_VSEPC] = { "vsepc", hmode, read_vsepc,
write_vsepc },
- [CSR_VSCAUSE] = { "vscause", hmode, read_vscause,
write_vscause },
- [CSR_VSTVAL] = { "vstval", hmode, read_vstval,
write_vstval },
- [CSR_VSATP] = { "vsatp", hmode, read_vsatp,
write_vsatp },
-
- [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2,
write_mtval2 },
- [CSR_MTINST] = { "mtinst", hmode, read_mtinst,
write_mtinst },
+ [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
write_hstatus,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
write_hedeleg,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HIDELEG] = { "hideleg", hmode, read_hideleg,
write_hideleg,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_HIE] = { "hie", hmode, read_hie, write_hie,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
write_hcounteren,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
write_htimedelta,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
write_htimedeltah,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+
+ [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
write_vsstatus,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
+ NULL, NULL, PRIV_VERSION_1_12_0 },
+ [CSR_VSIE] = { "vsie", hmode, read_vsie, write_vsie,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
write_vsscratch,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSCAUSE] = { "vscause", hmode, read_vscause,
write_vscause,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+
+ [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
+ [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0
},
/* Physical Memory Protection */
- [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
+ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
+ NULL, NULL, NULL, PRIV_VERSION_1_12_0 },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
--
2.30.2
[RFC 5/5] target/riscv: Enable privileged spec version 1.12, Atish Patra, 2022/01/20