Re: [RESEND] target/riscv: fix RV128 lq encoding

[Philipp Tomsich]

The cbo.* mnemonics share their opcode space with lq for those cases where rd == 0 ("brownfield" encodings).

"Major opcode" refers to inst[6:0] according to chapter 26.

In overlapping multi-group syntax, this would look like:

{

  # *** RV32 Zicbom Standard Extension ***

  cbo_clean  0000000 00001 ..... 010 00000 0001111 @sfence_vm

  cbo_flush  0000000 00010 ..... 010 00000 0001111 @sfence_vm

  cbo_inval  0000000 00000 ..... 010 00000 0001111 @sfence_vm

  # *** RV32 Zicboz Standard Extension ***

  cbo_zero   0000000 00100 ..... 010 00000 0001111 @sfence_vm

  # *** RVI128 lq ***

  lq       ............   ..... 010 ..... 0001111 @i

}

Instead of using a multigroup here, I would recommend that you take a look at https://patchwork.kernel.org/project/qemu-devel/list/?series=605340 where we have added a table of optional decoders — this could be used to split these off into separate decoders that are run before the regular decoder, if & only if Zicboc and/or Zicboz are enabled. 

Cheers,

Philipp.

On Tue, 18 Jan 2022 at 17:32, Christoph Muellner <cmuellner@linux.com> wrote:

If LQ has func3==010 and is located in the MISC-MEM opcodes,
then it conflicts with the CBO opcode space.
However, since LQ is specified as: "LQ is added to the MISC-MEM major
opcode", we have an implementation bug, because 'major opcode'
refers to func3, which must be 111.

This results in the following instruction encodings:

lq        ........ ........ .111.... .0001111
cbo_clean 00000000 0001.... .0100000 00001111
cbo_flush 00000000 0010.... .0100000 00001111
cbo_inval 00000000 0000.... .0100000 00001111
cbo_zero  00000000 0100.... .0100000 00001111
                             ^^^-func3
                                      ^^^^^^^-opcode

Signed-off-by: Christoph Muellner <cmuellner@linux.com>
---
 target/riscv/insn32.decode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..d3f798ca10 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -168,7 +168,7 @@ sraw     0100000 .....  ..... 101 ..... 0111011 @r

 # *** RV128I Base Instruction Set (in addition to RV64I) ***
 ldu      ............   ..... 111 ..... 0000011 @i
-lq       ............   ..... 010 ..... 0001111 @i
+lq       ............   ..... 111 ..... 0001111 @i
 sq       ............   ..... 100 ..... 0100011 @s
 addid    ............  .....  000 ..... 1011011 @i
 sllid    000000 ......  ..... 001 ..... 1011011 @sh6
--
2.34.1