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[PATCH v7 21/22] target/riscv: Enable uxl field write
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v7 21/22] target/riscv: Enable uxl field write |
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Date: |
Wed, 19 Jan 2022 13:18:23 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b11d92b51b..90f78eca65 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int
csrno,
{
uint64_t mstatus = env->mstatus;
uint64_t mask = 0;
+ RISCVMXL xl = riscv_cpu_mxl(env);
/* flush tlb on mstatus fields that affect VM */
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
- if (riscv_cpu_mxl(env) != MXL_RV32) {
+ if (xl != MXL_RV32) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
mask |= MSTATUS_MPV | MSTATUS_GVA;
+ if ((val & MSTATUS64_UXL) != 0) {
+ mask |= MSTATUS64_UXL;
+ }
}
mstatus = (mstatus & ~mask) | (val & mask);
- RISCVMXL xl = riscv_cpu_mxl(env);
if (xl > MXL_RV32) {
- /* SXL and UXL fields are for now read only */
+ /* SXL field is for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
- mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
}
env->mstatus = mstatus;
env->xl = cpu_recompute_xl(env);
@@ -907,7 +909,9 @@ static RISCVException read_sstatus(CPURISCVState *env, int
csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
-
+ if (env->xl != MXL_RV32) {
+ mask |= SSTATUS64_UXL;
+ }
/* TODO: Use SXL not MXL. */
*val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
return RISCV_EXCP_NONE;
@@ -917,6 +921,9 @@ static RISCVException write_sstatus(CPURISCVState *env, int
csrno,
target_ulong val)
{
target_ulong mask = (sstatus_v1_10_mask);
+ if (env->xl != MXL_RV32) {
+ mask |= SSTATUS64_UXL;
+ }
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
--
2.25.1
- [PATCH v7 11/22] target/riscv: Create current pm fields in env, (continued)
- [PATCH v7 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/19
- [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/19
- [PATCH v7 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/19
- [PATCH v7 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/19
- [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/19
- [PATCH v7 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/19
- [PATCH v7 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/19
- [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 21/22] target/riscv: Enable uxl field write,
LIU Zhiwei <=
- Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
[PATCH v7 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/19