[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v7 07/22] target/riscv: Extend pc for runtime pc write
From: |
LIU Zhiwei |
Subject: |
[PATCH v7 07/22] target/riscv: Extend pc for runtime pc write |
Date: |
Wed, 19 Jan 2022 13:18:09 +0800 |
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 736cf1d4e7..eac5f7bf03 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -355,7 +355,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = value;
+
+ if (env->xl == MXL_RV32) {
+ env->pc = (int32_t)value;
+ } else {
+ env->pc = value;
+ }
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@@ -363,7 +368,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- env->pc = tb->pc;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
}
static bool riscv_cpu_has_work(CPUState *cs)
@@ -384,7 +395,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
- env->pc = data[0];
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)data[0];
+ } else {
+ env->pc = data[0];
+ }
}
static void riscv_cpu_reset(DeviceState *dev)
--
2.25.1
- [PATCH v7 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2022/01/19
- [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2022/01/19
- [PATCH v7 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2022/01/19
- [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr, LIU Zhiwei, 2022/01/19
- [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 05/22] target/riscv: Create xl field in env, LIU Zhiwei, 2022/01/19
- [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write,
LIU Zhiwei <=
- [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/19
- [PATCH v7 09/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/19
- [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/19
- [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/19
- [PATCH v7 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/19
- [PATCH v7 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/19
- [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/19