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[PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening
From: |
frank . chang |
Subject: |
[PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns |
Date: |
Tue, 18 Jan 2022 09:45:11 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 08f25e3ce4..58f12366dd 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
return s->ext_zve64f ? s->sew <= MO_32 : true;
}
+static bool require_scale_zve64f(DisasContext *s)
+{
+ /* RVV + Zve64f = RVV. */
+ if (has_ext(s, RVV)) {
+ return true;
+ }
+
+ /* Zve64f doesn't support FP64. (Section 18.2) */
+ return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
/* Destination vector register group cannot overlap source mask register. */
static bool require_vm(int vm, int vd)
{
@@ -2333,7 +2344,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
- vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+ vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
/* OPFVV with WIDEN */
@@ -2372,7 +2384,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
- vext_check_ds(s, a->rd, a->rs2, a->vm);
+ vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
/* OPFVF with WIDEN */
@@ -2402,7 +2415,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
- vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+ vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
/* WIDEN OPFVV with WIDEN */
@@ -2441,7 +2455,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr
*a)
require_scale_rvf(s) &&
(s->sew != MO_8) &&
vext_check_isa_ill(s) &&
- vext_check_dd(s, a->rd, a->rs2, a->vm);
+ vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
/* WIDEN OPFVF with WIDEN */
@@ -2700,14 +2715,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr
*a)
static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
- require_rvf(s);
+ require_rvf(s) &&
+ require_zve64f(s);
}
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
require_scale_rvf(s) &&
- (s->sew != MO_8);
+ (s->sew != MO_8) &&
+ require_scale_zve64f(s);
}
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
@@ -2758,7 +2775,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
require_scale_rvf(s) &&
vext_check_isa_ill(s) &&
/* OPFV widening instructions ignore vs1 check */
- vext_check_ds(s, a->rd, a->rs2, a->vm);
+ vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+ require_scale_zve64f(s);
}
#define GEN_OPFXV_WIDEN_TRANS(NAME) \
--
2.31.1
- [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, (continued)
- [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2022/01/17
- [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2022/01/17
- [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2022/01/17
- [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2022/01/17
- [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns,
frank . chang <=
- [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2022/01/17
- [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, frank . chang, 2022/01/17
- Re: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, Alistair Francis, 2022/01/18