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[PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configura
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From: |
frank . chang |
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Subject: |
[PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns |
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Date: |
Tue, 18 Jan 2022 09:45:05 +0800 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c285c958b..5b47729a21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
{
TCGv s1, dst;
- if (!require_rvv(s) || !has_ext(s, RVV)) {
+ if (!require_rvv(s) ||
+ !(has_ext(s, RVV) || s->ext_zve64f)) {
return false;
}
@@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1,
TCGv s2)
{
TCGv dst;
- if (!require_rvv(s) || !has_ext(s, RVV)) {
+ if (!require_rvv(s) ||
+ !(has_ext(s, RVV) || s->ext_zve64f)) {
return false;
}
--
2.31.1
- [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2022/01/17
- [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns,
frank . chang <=
- [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2022/01/17
- [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2022/01/17
- [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2022/01/17
- [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2022/01/17
- [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2022/01/17