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Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv
From: |
Alistair Francis |
Subject: |
Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns |
Date: |
Tue, 18 Jan 2022 08:31:31 +1000 |
On Wed, Dec 29, 2021 at 12:37 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support all vector fixed-point arithmetic
> instructions, except that vsmul.vv and vsmul.vx are not supported
> for EEW=64 in Zve64*.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 658cfbe10e..a1e403fe86 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2121,8 +2121,31 @@ GEN_OPIVX_TRANS(vasub_vx, opivx_check)
> GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
>
> /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
> -GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
> -GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
> +
> +static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
> +{
> + /*
> + * All Zve* extensions support all vector fixed-point arithmetic
> + * instructions, except that vsmul.vv and vsmul.vx are not supported
> + * for EEW=64 in Zve64*. (Section 18.2)
> + */
> + return opivv_check(s, a) &&
> + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
> +static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
> +{
> + /*
> + * All Zve* extensions support all vector fixed-point arithmetic
> + * instructions, except that vsmul.vv and vsmul.vx are not supported
> + * for EEW=64 in Zve64*. (Section 18.2)
> + */
> + return opivx_check(s, a) &&
> + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
> +}
> +
> +GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
> +GEN_OPIVX_TRANS(vsmul_vx, vsmul_vx_check)
>
> /* Vector Single-Width Scaling Shift Instructions */
> GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
> --
> 2.31.1
>
>
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- Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns,
Alistair Francis <=