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[PATCH v7 06/23] target/riscv: Add AIA cpu feature
From: |
Anup Patel |
Subject: |
[PATCH v7 06/23] target/riscv: Add AIA cpu feature |
Date: |
Mon, 17 Jan 2022 18:58:09 +0530 |
From: Anup Patel <anup.patel@wdc.com>
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2c04826496..71a2fd1da7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -77,7 +77,8 @@ enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
- RISCV_FEATURE_MISA
+ RISCV_FEATURE_MISA,
+ RISCV_FEATURE_AIA
};
#define PRIV_VERSION_1_10_0 0x00011000
--
2.25.1
- [PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART, (continued)
- [PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2022/01/17
- [PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2022/01/17
- [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 22/23] docs/system: riscv: Document AIA options for virt machine, Anup Patel, 2022/01/17
- [PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs, Anup Patel, 2022/01/17
- [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2022/01/17
- [PATCH v7 06/23] target/riscv: Add AIA cpu feature,
Anup Patel <=
- [PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2022/01/17