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[PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the publi
From: |
Yifei Jiang |
Subject: |
[PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface |
Date: |
Wed, 12 Jan 2022 16:13:18 +0800 |
Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/kvm.c | 133 +++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 1 +
2 files changed, 134 insertions(+)
create mode 100644 target/riscv/kvm.c
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
new file mode 100644
index 0000000000..687dd4b621
--- /dev/null
+++ b/target/riscv/kvm.c
@@ -0,0 +1,133 @@
+/*
+ * RISC-V implementation of KVM hooks
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include <linux/kvm.h>
+
+#include "qemu-common.h"
+#include "qemu/timer.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "sysemu/kvm_int.h"
+#include "cpu.h"
+#include "trace.h"
+#include "hw/pci/pci.h"
+#include "exec/memattrs.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "qemu/log.h"
+#include "hw/loader.h"
+
+const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
+ KVM_CAP_LAST_INFO
+};
+
+int kvm_arch_get_registers(CPUState *cs)
+{
+ return 0;
+}
+
+int kvm_arch_put_registers(CPUState *cs, int level)
+{
+ return 0;
+}
+
+int kvm_arch_release_virq_post(int virq)
+{
+ return 0;
+}
+
+int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
+ uint64_t address, uint32_t data, PCIDevice *dev)
+{
+ return 0;
+}
+
+int kvm_arch_destroy_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+unsigned long kvm_arch_vcpu_id(CPUState *cpu)
+{
+ return cpu->cpu_index;
+}
+
+void kvm_arch_init_irq_routing(KVMState *s)
+{
+}
+
+int kvm_arch_init_vcpu(CPUState *cs)
+{
+ return 0;
+}
+
+int kvm_arch_msi_data_to_gsi(uint32_t data)
+{
+ abort();
+}
+
+int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
+ int vector, PCIDevice *dev)
+{
+ return 0;
+}
+
+int kvm_arch_init(MachineState *ms, KVMState *s)
+{
+ return 0;
+}
+
+int kvm_arch_irqchip_create(KVMState *s)
+{
+ return 0;
+}
+
+int kvm_arch_process_async_events(CPUState *cs)
+{
+ return 0;
+}
+
+void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
+{
+}
+
+MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
+{
+ return MEMTXATTRS_UNSPECIFIED;
+}
+
+bool kvm_arch_stop_on_emulation_error(CPUState *cs)
+{
+ return true;
+}
+
+int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+{
+ return 0;
+}
+
+bool kvm_arch_cpu_check_are_resettable(void)
+{
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a32158da93..95340b44aa 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -20,6 +20,7 @@ riscv_ss.add(files(
'translate.c',
'm128_helper.c'
))
+riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
--
2.19.1
- [PATCH v5 00/13] Add riscv kvm accel support, Yifei Jiang, 2022/01/12
- [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h, Yifei Jiang, 2022/01/12
- [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface,
Yifei Jiang <=
- [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 2022/01/12
- [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2022/01/12
- [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers, Yifei Jiang, 2022/01/12
- [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 2022/01/12
- [PATCH v5 07/13] target/riscv: Support setting external interrupt by KVM, Yifei Jiang, 2022/01/12
- [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2022/01/12
- [PATCH v5 09/13] target/riscv: Add host cpu type, Yifei Jiang, 2022/01/12
- [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 2022/01/12
- [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 2022/01/12