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Re: [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation |
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Date: |
Mon, 20 Dec 2021 15:38:13 +0800 |
On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> When realising the SoC use error_fatal instead of error_abort as the
> process can fail and report useful information to the user.
>
> Currently a user can see this:
>
> $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
> none -drive if=pflash
> QEMU 6.1.93 monitor - type 'help' for more information
> (qemu) Unexpected error in sifive_u_otp_realize() at
> ../hw/misc/sifive_u_otp.c:229:
> qemu-system-riscv64: OTP drive size < 16K
> Aborted (core dumped)
>
> Which this patch addresses
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reported-by: Markus Armbruster <armbru@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Markus Armbruster <armbru@redhat.com>
> ---
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/opentitan.c | 2 +-
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function, (continued)
- [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/15
- [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/15
- [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/15
- [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/15
- [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/15
- Re: [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation,
Bin Meng <=
- [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2021/12/15
- Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Bin Meng, 2021/12/20
- [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency, Alistair Francis, 2021/12/15