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[PATCH v7 02/18] exec/memop: Adding signed quad and octo defines
From: |
Frédéric Pétrot |
Subject: |
[PATCH v7 02/18] exec/memop: Adding signed quad and octo defines |
Date: |
Mon, 13 Dec 2021 17:38:18 +0100 |
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
include/exec/memop.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 72c2f0ff3d..2a885f3917 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -86,28 +86,35 @@ typedef enum MemOp {
MO_UW = MO_16,
MO_UL = MO_32,
MO_UQ = MO_64,
+ MO_UO = MO_128,
MO_SB = MO_SIGN | MO_8,
MO_SW = MO_SIGN | MO_16,
MO_SL = MO_SIGN | MO_32,
+ MO_SQ = MO_SIGN | MO_64,
+ MO_SO = MO_SIGN | MO_128,
MO_LEUW = MO_LE | MO_UW,
MO_LEUL = MO_LE | MO_UL,
MO_LEUQ = MO_LE | MO_UQ,
MO_LESW = MO_LE | MO_SW,
MO_LESL = MO_LE | MO_SL,
+ MO_LESQ = MO_LE | MO_SQ,
MO_BEUW = MO_BE | MO_UW,
MO_BEUL = MO_BE | MO_UL,
MO_BEUQ = MO_BE | MO_UQ,
MO_BESW = MO_BE | MO_SW,
MO_BESL = MO_BE | MO_SL,
+ MO_BESQ = MO_BE | MO_SQ,
#ifdef NEED_CPU_H
MO_TEUW = MO_TE | MO_UW,
MO_TEUL = MO_TE | MO_UL,
MO_TEUQ = MO_TE | MO_UQ,
+ MO_TEUO = MO_TE | MO_UO,
MO_TESW = MO_TE | MO_SW,
MO_TESL = MO_TE | MO_SL,
+ MO_TESQ = MO_TE | MO_SQ,
#endif
MO_SSIZE = MO_SIZE | MO_SIGN,
--
2.34.1
- [PATCH v7 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/12/13
- [PATCH v7 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 02/18] exec/memop: Adding signed quad and octo defines,
Frédéric Pétrot <=
- [PATCH v7 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 2021/12/13
- [PATCH v7 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/12/13
- [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/12/13
- [PATCH v7 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/12/13