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[PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift inst
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From: |
frank . chang |
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Subject: |
[PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions |
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Date: |
Fri, 10 Dec 2021 15:56:41 +0800 |
From: Frank Chang <frank.chang@sifive.com>
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index b43234ed3f..03716ad706 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2030,8 +2030,8 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
-GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, IMM_TRUNC_SEW, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, IMM_TRUNC_SEW, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
--
2.31.1
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions, (continued)
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/12/10
- [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/12/10
- [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/12/10
- [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10
- [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/12/10
- [PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/12/10
- [PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/12/10
- [PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions,
frank . chang <=
- [PATCH v11 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/12/10
- [PATCH v11 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/12/10
- [PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/12/10
- [PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/12/10
- [PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/12/10
- [PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/12/10
- [PATCH v11 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/12/10
- [PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/12/10
- [PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/12/10