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[PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructio
From: |
frank . chang |
Subject: |
[PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions |
Date: |
Fri, 10 Dec 2021 15:56:17 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
target/riscv/vector_helper.c | 4 ----
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4df2aa9cdd..d139c0aade 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 3645bb9635..9206e6f06c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2731,7 +2731,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s) && \
+ require_vm(a->vm, a->rd) && \
+ (a->rd != a->rs2)) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f97783acf0..b0dc971a86 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4260,7 +4260,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.31.1
- [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions, (continued)
- [PATCH v11 20/77] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/12/10
- [PATCH v11 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/12/10
- [PATCH v11 21/77] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2021/12/10
- [PATCH v11 24/77] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/12/10
- [PATCH v11 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/12/10
- [PATCH v11 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/12/10
- [PATCH v11 28/77] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/12/10
- [PATCH v11 27/77] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/12/10
- [PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/12/10
- [PATCH v11 29/77] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/12/10
- [PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions,
frank . chang <=
- [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/12/10
- [PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/12/10
- [PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/12/10
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/12/10
- [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/12/10
- [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/12/10
- [PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/12/10