[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target
|
From: |
Frédéric Pétrot |
|
Subject: |
Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target |
|
Date: |
Mon, 29 Nov 2021 14:24:00 +0100 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 |
On 29/11/2021 13:13, Richard Henderson wrote:
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and suggestions.
v6:
- support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit
executables (no more qemu-system-riscv128)
- remove useless (and buggy) big-endian support in lq/sq
This also fails make check. With
../qemu/configure --enable-debug
--target-list=riscv64-linux-user,riscv64-softmmu,riscv32-softmmu,riscv32-linux-user
Ah! Indeed, sorry for the mess, I indeed forgot about linux-user.
Frédéric
watch qemu-iotest 040 fail.
r~
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
- [PATCH v6 14/18] target/riscv: support for 128-bit M extension, (continued)
- [PATCH v6 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/28
- [PATCH v6 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/28
- [PATCH v6 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/28
- [PATCH v6 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/28
- [PATCH v6 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/28
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Richard Henderson, 2021/11/29
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Richard Henderson, 2021/11/29
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target,
Frédéric Pétrot <=