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[PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field
From: |
frank . chang |
Subject: |
[PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field |
Date: |
Mon, 29 Nov 2021 11:02:26 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 83f4dbd8241..bc149add6ce 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -643,7 +643,7 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
val &= env->misa_ext_mask;
/* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
--
2.25.1
- [PATCH v10 59/77] target/riscv: rvv-1.0: floating-point min/max instructions, (continued)
- [PATCH v10 59/77] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/11/28
- [PATCH v10 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/11/28
- [PATCH v10 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/11/28
- [PATCH v10 63/77] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/11/28
- [PATCH v10 60/77] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/11/28
- [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/11/28
- [PATCH v10 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/11/28
- [PATCH v10 66/77] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/11/28
- [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/11/28
- [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/11/28
- [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field,
frank . chang <=
- [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/11/28
- [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/11/28
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/11/28
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/11/28
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/11/28
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/11/28
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/11/28
- [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/11/28