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[PATCH v6 04/18] target/riscv: additional macros to check instruction su
From: |
Frédéric Pétrot |
Subject: |
[PATCH v6 04/18] target/riscv: additional macros to check instruction support |
Date: |
Sun, 28 Nov 2021 14:57:05 +0100 |
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..2718ff15a1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -368,10 +368,22 @@ EX_SH(12)
} \
} while (0)
-#define REQUIRE_64BIT(ctx) do { \
- if (get_xl(ctx) < MXL_RV64) { \
- return false; \
- } \
+#define REQUIRE_64BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV64) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_128BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV128) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_64_OR_128BIT(ctx) do { \
+ if (get_xl(ctx) == MXL_RV32) { \
+ return false; \
+ } \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
--
2.34.0
- [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/11/28
- [PATCH v6 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/11/28
- [PATCH v6 04/18] target/riscv: additional macros to check instruction support,
Frédéric Pétrot <=
- [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/11/28
- [PATCH v6 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2021/11/28
- [PATCH v6 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/28
- [PATCH v6 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/28
- [PATCH v6 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/28