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[PATCH v5 14/22] target/riscv: Split out the vill from vtype
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 14/22] target/riscv: Split out the vill from vtype |
Date: |
Thu, 25 Nov 2021 15:39:43 +0800 |
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c | 13 ++++++++++++-
target/riscv/machine.c | 5 +++--
target/riscv/vector_helper.c | 3 ++-
5 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3986a2164d..1e56405243 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -119,6 +119,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ bool vill;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 91b84be48f..7945f687b4 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -77,8 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 68da5d2173..3f284090fc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -286,7 +286,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int
csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vtype;
+ uint64_t vill;
+ switch (env->xl) {
+ case MXL_RV32:
+ vill = (uint32_t)env->vill << 31;
+ break;
+ case MXL_RV64:
+ vill = (uint64_t)env->vill << 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ *val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 10a0f34f37..cf71a5ad33 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -124,8 +124,8 @@ static bool vector_needed(void *opaque)
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12c31aa4b4..b02ccefa4d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -38,7 +38,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
--
2.25.1
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, (continued)
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype,
LIU Zhiwei <=
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/25
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/25
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 22/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/25