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[PATCH v5 00/22] Support UXL filed in xstatus

From: LIU Zhiwei
Subject: [PATCH v5 00/22] Support UXL filed in xstatus
Date: Thu, 25 Nov 2021 15:39:29 +0800

In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.

The patch set v5 fix an error in v4: miss to select gdb core xml according
to mxl. Besides, add xl field in CPURISCVState, so that we can remove many
redundant riscv_cpu_xl calls. It will also benefit other extensions.
The last new change is to calculate the number of PMP configuration in
one pmpcfgx CSR according to mxl.

Patch 1, 4, 21, have not been reviewed. Others have been reviewed or acked.

  Add xl field in env to clear up redundant riscv_cpu_xl
  Adjust pmpcfg access with mxl
  Select gdb core xml according to mxl 

  Support SSTATUS64_UXL write
  Bump vmstate version for vill split

  Merge gen_pm_adjust_address into a canonical address function
  Adjust address for RVA with XLEN
  Split pm_enabled into pm_mask_enabled and pm_base_enabled
  Replace array of pm tcg globals with one scalar tcg global
  Split and change patch sequence

  Split out vill from vtype
  Remove context switch when xlen changes at exception
  Use XL instead of OL in many places
  Use pointer masking and XLEN for vector address
  Define an common fuction to calculate address for lds

LIU Zhiwei (22):
  target/riscv: Adjust pmpcfg access with mxl
  target/riscv: Don't save pc when exception return
  target/riscv: Sign extend pc for different XLEN
  target/riscv: Create xl field in env
  target/riscv: Ignore the pc bits above XLEN
  target/riscv: Extend pc for runtime pc write
  target/riscv: Use gdb xml according to max mxlen
  target/riscv: Relax debug check for pm write
  target/riscv: Adjust csr write mask with XLEN
  target/riscv: Create current pm fields in env
  target/riscv: Alloc tcg global for cur_pm[mask|base]
  target/riscv: Calculate address according to XLEN
  target/riscv: Split pm_enabled into mask and base
  target/riscv: Split out the vill from vtype
  target/riscv: Fix RESERVED field length in VTYPE
  target/riscv: Adjust vsetvl according to XLEN
  target/riscv: Remove VILL field in VTYPE
  target/riscv: Ajdust vector atomic check with XLEN
  target/riscv: Fix check range for first fault only
  target/riscv: Adjust vector address with mask
  target/riscv: Adjust scalar reg in vector with XLEN
  target/riscv: Enable uxl field write

 target/riscv/cpu.c                            | 27 ++++++-
 target/riscv/cpu.h                            | 19 ++++-
 target/riscv/cpu_bits.h                       |  2 +
 target/riscv/cpu_helper.c                     | 65 ++++++++++++----
 target/riscv/csr.c                            | 63 ++++++++++++++-
 target/riscv/gdbstub.c                        | 71 ++++++++++++-----
 target/riscv/helper.h                         |  4 +-
 .../riscv/insn_trans/trans_privileged.c.inc   |  7 +-
 target/riscv/insn_trans/trans_rva.c.inc       |  9 +--
 target/riscv/insn_trans/trans_rvd.c.inc       | 19 +----
 target/riscv/insn_trans/trans_rvf.c.inc       | 19 +----
 target/riscv/insn_trans/trans_rvi.c.inc       | 22 +-----
 target/riscv/insn_trans/trans_rvv.c.inc       | 47 +++++++----
 target/riscv/machine.c                        | 20 ++++-
 target/riscv/op_helper.c                      |  7 +-
 target/riscv/pmp.c                            | 12 +--
 target/riscv/translate.c                      | 77 +++++++++----------
 target/riscv/vector_helper.c                  | 37 +++++----
 18 files changed, 333 insertions(+), 194 deletions(-)


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