Re: [PATCH v5 04/18] target/riscv: additional macros to check instruction support

[Alistair Francis]

On Sat, Nov 13, 2021 at 1:08 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
>
> Given that the 128-bit version of the riscv spec adds new instructions, and
> that some instructions that were previously only available in 64-bit mode
> are now available for both 64-bit and 128-bit, we added new macros to check
> for the processor mode during translation.
> Although RV128 is a superset of RV64, we keep for now the RV64 only tests
> for extensions other than RVI and RVM.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1d57bc97b5..d98bde9b6b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -368,10 +368,22 @@ EX_SH(12)
>      }                              \
>  } while (0)
>
> -#define REQUIRE_64BIT(ctx) do {    \
> -    if (get_xl(ctx) < MXL_RV64) {  \
> -        return false;              \
> -    }                              \
> +#define REQUIRE_64BIT(ctx) do {     \
> +    if (get_xl(ctx) != MXL_RV64) { \
> +        return false;               \
> +    }                               \
> +} while (0)
> +
> +#define REQUIRE_128BIT(ctx) do {    \
> +    if (get_xl(ctx) != MXL_RV128) { \
> +        return false;               \
> +    }                               \
> +} while (0)
> +
> +#define REQUIRE_64_OR_128BIT(ctx) do { \
> +    if (get_xl(ctx) == MXL_RV32) {     \
> +        return false;                  \
> +    }                                  \
>  } while (0)
>
>  static int ex_rvc_register(DisasContext *ctx, int reg)
> --
> 2.33.1
>
>