Re: [PATCH v4 01/20] target/riscv: Don't save pc when exception return

[Alistair Francis]

On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> As pc will be written by the xepc in exception return, just ignore
> pc in translation.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                          | 4 ++--
>  target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
>  target/riscv/op_helper.c                       | 4 ++--
>  3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index c7a5376227..c5098380dd 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int)
>  DEF_HELPER_3(csrw, void, env, int, tl)
>  DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
>  #ifndef CONFIG_USER_ONLY
> -DEF_HELPER_2(sret, tl, env, tl)
> -DEF_HELPER_2(mret, tl, env, tl)
> +DEF_HELPER_1(sret, tl, env)
> +DEF_HELPER_1(mret, tl, env)
>  DEF_HELPER_1(wfi, void, env)
>  DEF_HELPER_1(tlb_flush, void, env)
>  #endif
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc 
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 75c6ef80a6..6077bbbf11 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
>  static bool trans_sret(DisasContext *ctx, arg_sret *a)
>  {
>  #ifndef CONFIG_USER_ONLY
> -    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> -
>      if (has_ext(ctx, RVS)) {
> -        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> +        gen_helper_sret(cpu_pc, cpu_env);
>          tcg_gen_exit_tb(NULL, 0); /* no chaining */
>          ctx->base.is_jmp = DISAS_NORETURN;
>      } else {
> @@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
>  static bool trans_mret(DisasContext *ctx, arg_mret *a)
>  {
>  #ifndef CONFIG_USER_ONLY
> -    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> -    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
> +    gen_helper_mret(cpu_pc, cpu_env);
>      tcg_gen_exit_tb(NULL, 0); /* no chaining */
>      ctx->base.is_jmp = DISAS_NORETURN;
>      return true;
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index ee7c24efe7..095d39671b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
>
>  #ifndef CONFIG_USER_ONLY
>
> -target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> +target_ulong helper_sret(CPURISCVState *env)
>  {
>      uint64_t mstatus;
>      target_ulong prev_priv, prev_virt;
> @@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong 
> cpu_pc_deb)
>      return retpc;
>  }
>
> -target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> +target_ulong helper_mret(CPURISCVState *env)
>  {
>      if (!(env->priv >= PRV_M)) {
>          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> --
> 2.25.1
>
>