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[PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol |
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Date: |
Mon, 1 Nov 2021 18:01:40 +0800 |
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
target/riscv/vector_helper.c | 6 ++++--
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5cd9b802df..947a58d7ca 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -853,7 +853,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t
vs2, uint32_t vm,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- src1 = get_gpr(s, rs1, EXT_NONE);
+ src1 = get_gpr(s, rs1, EXT_SIGN);
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
@@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+ TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2686,7 +2687,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
}
t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ tcg_gen_extu_tl_i64(t1, src1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
done:
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 451688c328..5bdbbf7c71 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4763,6 +4763,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t mlen = vext_mlen(desc); \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t olen = 16 << vext_ol(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4771,7 +4772,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
continue; \
} \
if (i == 0) { \
- *((ETYPE *)vd + H(i)) = s1; \
+ *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
} else { \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
@@ -4792,6 +4793,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t mlen = vext_mlen(desc); \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
+ uint32_t olen = 16 << vext_ol(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
@@ -4800,7 +4802,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
continue; \
} \
if (i == vl - 1) { \
- *((ETYPE *)vd + H(i)) = s1; \
+ *((ETYPE *)vd + H(i)) = adjust_addr(s1, olen); \
} else { \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
--
2.25.1
- Re: [PATCH 09/13] target/riscv: Adjust vector address with ol, (continued)
[PATCH 07/13] target/riscv: Ajdust vector atomic check with ol, LIU Zhiwei, 2021/11/01
[PATCH 06/13] target/riscv: Adjust vsetvl according to ol, LIU Zhiwei, 2021/11/01
[PATCH 13/13] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/01
[PATCH 10/13] target/riscv: Adjust scalar reg in vector with ol,
LIU Zhiwei <=
[PATCH 08/13] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/01