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[PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_wa
From: |
Bin Meng |
Subject: |
[PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() |
Date: |
Sat, 30 Oct 2021 21:55:13 +0800 |
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..532c148a80 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -92,6 +92,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
- [PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs, Bin Meng, 2021/10/30
- [PATCH v2 1/7] target/riscv: Add initial support for native debug, Bin Meng, 2021/10/30
- [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2021/10/30
- [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2021/10/30
- [PATCH v2 2/7] target/riscv: machine: Add debug state description, Bin Meng, 2021/10/30
- [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(),
Bin Meng <=
- [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2021/10/30
- [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs, Bin Meng, 2021/10/30